Walsh transform realization for microprocessor implementation of distance protection

In recent years there has been a growing trend towards application of digital methods to power line relaying. This has resulted in the design and implementation of very fast distance relays, operating in conjunction with modern circuit-breakers, to meet the growing system requirements of ultra-high-speed fault clearance. This paper describes simple computational procedures, based on the fast Walsh-Hadamard transform (FWHT), for real-time calculation of the fault impedance of transmission lines. These algorithms are implemented on an Intel 8086 microprocessor using 16 samples per cycle of current and voltage signals. Special attention has been paid to the reduction of errors produced by DC offset and by high frequency components in the currents and voltages. A quadrilateral characteristic has been used in the relay for trip decision. Other characteristics such as restricted admittance can also be realized easily, thus providing flexibility to the relay. The hardware and software architecture of the relay is described. The paper also presents the results of tests carried out on the relay using simulated fault data. A tripping signal is sent in less than three-quarters of a cycle of a 50 Hz system for different types of faults. The relay is also evaluated for its dynamic performance characteristics which include directional discrimination, variation of speed and accuracy with fault level, distance to fault, transient components, etc.