Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits

Power dissipation in high performance systems requires more expensive packaging. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field. As the density and operating speed of CMOS VLSI chip increases, static power dissipation becomes more significant. This is due to the leakage current when the transistor is off this is threshold voltage dependent. This can be observed in the combinational and sequential circuits. Static power reduction techniques are achieved by means of operating the transistor either in Cut-off or in Saturation region completely and avoiding the clock in unnecessary circuits. In this article, Dual sub-threshold voltage supply technique is used, to operate the transistor under off state or either in on state by applying some voltage at the gate of the MOS transistor. This static power reduction technique is to digital circuits, so that the power dissipation is reduced, and the performance of the circuit is increased. The designed circuits can be simulated by using Mentor Graphics Backend Tool.