Gate-last integration on planar FDSOI for low-V sub(Tp) and low-EOT MOSFETs

Gate-last integration on planar FDSOI for low-V sub(Tp) and low-EOT MOSFETs

We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg = 15 nm and active widths of W= 80 nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of V sub(Tp) = -0.2 V and one decade gate current (J sub(G)) g...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Microelectronic engineering 2013-09, Vol.109, p.306-309
Hauptverfasser: Morvan, S, Andrieu, F, Leroux, C, Garros, X, Casse, M, Martin, F, Gassilloud, R, Morand, Y, Le Royer, C, Besson, P, Roure, M-C, Euvrard, C, Rivoire, M, Seignard, A
Format: Artikel
Sprache:eng
Schlagworte:
Benchmarking
Electric potential
Equivalence
Gain
Gates
MOSFETs
Oxides
Voltage
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg = 15 nm and active widths of W= 80 nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of V sub(Tp) = -0.2 V and one decade gate current (J sub(G)) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (V sub(FB)) shift under stress.
ISSN:0167-9317