A digitally calibrated CMOS RMS power detector for RF automatic gain control

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency （RF） root-mean-square （RMS） power detector for high accuracy RF automatic gain control （AGC）. The proposed RMS power detector demonstrates accurate power detection in the presence of process, supply voltage, and temperature （PVT） variations by employing a digital calibration scheme. It also consumes low power and occupies a small chip area. The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz. Implemented in a 0.18 μm CMOS process and occupying a small die area of 263 × 214 μm2, the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.