FPGA Implementation of an LFSR based Pseudorandom Pattern Generator for MEMS Testing

Recent strides in programmable logic density, speed and hardware description language (HDL) have empowered the engineer with the ability to implement high-performance digital functionality within field programmable gate array (FPGA). Linear feedback shift resister (LFSR) has become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers and integrated circuits (ICs). This paper presents the FPGA implementation of an LFSR based pseudorandom pattern generator. This LFSR has the characteristics of high speed, low power consumption and it is especially suited in processing environment where uniform distribution random numbers are required. A typical application of the pattern generator considered in this work is the testing of micro-electro-mechanical-system (MEMS), where low power consumption is required. Very high speed integrated circuit HDL (VHDL) was used to implement the LFSR on FPGA. A testbench in VHDL was used to verify the correctness of the design. The compiled VHDL code was been synthesized into gate level. Area and timing optimization were done to achieve a very low gate count of 436 and increase the design speed to 178MHz Mentor Graphics and Xilinx ISE 6, electronic design automation (EDA) tool suite and DIGILENT D2SB PROTO BOARD were used for the overall FPGA implementation process.