Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on nuclear science 2006-12, Vol.53 (6), p.3512-3517
Hauptverfasser: Heidel, D.F., Rodbell, K.P., Oldiges, P., Gordon, M.S., Tang, H.H.K., Cannon, E.H., Plettner, C.
Format: Artikel
Sprache:eng
Schlagworte:
Beams (radiation)
Charge
Charge deposition
Charge measurement
Circuit simulation
Circuits
CMOS technology
Collimation
Critical charge
Ion accelerators
Latches
Particle beams
Qcrit
Semiconductor device modeling
SER
Silicon on insulator technology
Single event upset
single event upsets
SOI
SPICE
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2006.886223