Process integration of fine pitch Cu redistribution wiring and SnCu micro-bumping for power efficient LSI devices with high-bandwidth stacked DRAM

[Display omitted] ► Process integration of 10μm pitch Cu redistribution wiring has been successfully executed on DRAM wafers with high yield. ► High accuracy of 40μm pitch SnCu bump joints has been verified by mass reflow bonding due to self-aligning effect. ► (Cu, Ni)6Sn5 intermetallic phase has been confirmed to work as a good diffusion barrier at Ni UBM/SnCu bump interface. ► Reliability stressing on packaged chip-on-chip stacks reveals no failures attributed to micro SnCu joints. This paper deals with the process integration to produce a high performance processor with a large-scale and high-bandwidth DRAM chip stacked. Ten micrometres pitch Cu redistribution wiring has been implemented on 12 in. DRAM wafers to relocate the Al bond pads where 40μm pitch SnCu bumps are formed for a large number of I/Os of the memory interface. A phenol-melamine based resin film which is curable at less than 250°C can be used so as to avert detraction from memory retention yield as well as to insulate the Cu lines, leading to reduction of wafer warpage in an effort to enable fine pitch lithography. In a chip-on-chip joining process, the logic chip is interconnected with the DRAM chip with a less than 1μm accuracy by mass reflow bonding of the SnCu micro-bumps on both of the chips, revealing the self-aligning effect of the solder bumps. No failures have been observed after reliability stressing on the packaged two-chip stack. The present process integration has been qualified for the mass producing line to provide some merchant LSI devices and will be viable to future generation devices with more chips stacked using through Si via technology.