Logical Effort to Study the Performance of 32-bit Heterogeneous Adder

The method of Logical Effort is an easy way to estimate the delay in a CMOS circuit. In this work application of Logical Effort on transistor level analysis of 32-bit heterogeneous adder architecture is designed and presented. Heterogeneous architecture consists of concatenation of four different su...

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Veröffentlicht in:	International journal of computer applications 2013-01, Vol.65 (16)
Hauptverfasser:	Agarwal, Neha, Anand, Satyajit
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Circuits CMOS Computer simulation Delay Design engineering Ripples
Online-Zugang:	Volltext
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