A 19 nm 112.8 mm 2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

A 64 Gb MLC NAND flash memory in 19 nm CMOS technology has been developed. By adopting one-sided all bit line (ABL) architecture, the single cell array configuration, bit line bias acceleration (BLBA) and BC states first program algorithm, the smallest 64 Gb die size in 2 bit/cell is achieved with h...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2013-01, Vol.48 (1), p.159-167
Hauptverfasser:	Kanda, Kazushige, Shibata, Noboru, Hisada, Toshiki, Isobe, Katsuaki, Sato, Manabu, Shimizu, Yui, Shimizu, Takahiro, Sugimoto, Takahiro, Kobayashi, Tomohiro, Kanagawa, Naoaki, Kajitani, Yasuyuki, Ogawa, Takeshi, Iwasa, Kiyoaki, Kojima, Masatsugu, Suzuki, Toshihiro, Suzuki, Yuya, Sakai, Shintaro, Fujimura, Tomofumi, Utsunomiya, Yuko, Hashimoto, Toshifumi, Kobayashi, Naoki, Matsumoto, Yuuki, Inoue, Satoshi, Suzuki, Yoshinao, Honda, Yasuhiko, Kato, Yosuke, Zaitsu, Shingo, Chibvongodze, Hardwell, Watanabe, Mitsuyuki, Ding, Hong, Ookuma, Naoki, Yamashita, Ryuji
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Architecture Arrays Bias Circuits CMOS Flash memory (computers) High speed
Online-Zugang:	Volltext
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Beschreibung
Zusammenfassung:	A 64 Gb MLC NAND flash memory in 19 nm CMOS technology has been developed. By adopting one-sided all bit line (ABL) architecture, the single cell array configuration, bit line bias acceleration (BLBA) and BC states first program algorithm, the smallest 64 Gb die size in 2 bit/cell is achieved with high performance of 15 MB/s program throughput. Program suspend and erase suspend functions are introduced to improve the read latency. High speed toggle mode interface of 400 Mbit/sec/pin at VCCQ = 1.8 V is also realized.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2012.2215094