Analyzing of Pseudo-Ring Memory Self- Testing Schemes with Algorithms

In this paper, scan and ring schemes of the pseudo-ring memory self-testing are investigated. Both schemes are based on emulation of the linear or nonlinear feedback shiftregister by memory itself. Peculiarities of the pseudo-ring schemes implementation for multi-port and embedded memories, and for register file are described. It is shown that only small additional logic is required and allows microcontrollers at-speed testing. Moreover, posteriori values are given for some types of memories faults coverage when pseudo-ring testing schemes are applied.