Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement
The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the th...
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| Veröffentlicht in: | Science China. Technological sciences 2012-03, Vol.55 (3), p.588-593 |
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| container_title | Science China. Technological sciences |
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| creator | Yang, XiaoNan Zhang, ManHong Wang, Yong Huo, ZongLiang Long, ShiBing Zhang, Bo Liu, Jing Liu, Ming |
| description | The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined. |
| doi_str_mv | 10.1007/s11431-011-4694-4 |
| format | Article |
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CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.</description><identifier>ISSN: 1674-7321</identifier><identifier>EISSN: 1869-1900</identifier><identifier>DOI: 10.1007/s11431-011-4694-4</identifier><language>eng</language><publisher>Heidelberg: SP Science China Press</publisher><subject>Data storage ; Density ; Engineering ; Memory devices ; Oxides ; Poisson equation ; Schroedinger equation ; Threshold voltage ; Tunneling ; 内存 ; 器件 ; 循环过程 ; 电子陷阱 ; 电容 ; 电流测量 ; 纳米 ; 阈值电压</subject><ispartof>Science China. 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Technological sciences</title><addtitle>Sci. China Technol. Sci</addtitle><addtitle>SCIENCE CHINA Technological Sciences</addtitle><description>The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.</description><subject>Data storage</subject><subject>Density</subject><subject>Engineering</subject><subject>Memory devices</subject><subject>Oxides</subject><subject>Poisson equation</subject><subject>Schroedinger equation</subject><subject>Threshold voltage</subject><subject>Tunneling</subject><subject>内存</subject><subject>器件</subject><subject>循环过程</subject><subject>电子陷阱</subject><subject>电容</subject><subject>电流测量</subject><subject>纳米</subject><subject>阈值电压</subject><issn>1674-7321</issn><issn>1869-1900</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><recordid>eNp9kMFO3DAQQCPUSkV0P6A3c-Pi1hPbcXxECAoSUi9wtmadydYosRc7QVq-Hq8W9VhfZg7veaTXND9A_AQhzK8CoCRwAcBVZxVXZ8059J3lYIX4UvfOKG5kC9-aTSkvoj7ZWwHqvAnXEafDe4g7tmTcsx1FyriEFFmIrIQp-BR5xJh8PpQFJzbTnPKBDfQWPBW2lqPrcY8-LBg9MYwD82vOFJcKY1kzzXX_3nwdcSq0-ZwXzfPd7dPNPX_88_vh5vqRe6nMwkGOUsottKjBmmH0YHAYRO9bJEKPejBd2_txK7fb0ejejqPXkrTSuiNPQl40V6d_9zm9rlQWN4fiaZowUlqLAyGhtVq0qqJwQn1OpWQa3T6HGfOhQu5Y1p3KulrWHcu6o9OenFLZuKPsXtKaa8TyX-ny89DfFHev1ft3SQmrpbFWfgDwdom4</recordid><startdate>20120301</startdate><enddate>20120301</enddate><creator>Yang, XiaoNan</creator><creator>Zhang, ManHong</creator><creator>Wang, Yong</creator><creator>Huo, ZongLiang</creator><creator>Long, ShiBing</creator><creator>Zhang, Bo</creator><creator>Liu, Jing</creator><creator>Liu, Ming</creator><general>SP Science China Press</general><scope>2RA</scope><scope>92L</scope><scope>CQIGP</scope><scope>W92</scope><scope>~WA</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SR</scope><scope>7TB</scope><scope>8BQ</scope><scope>8FD</scope><scope>FR3</scope><scope>JG9</scope><scope>KR7</scope></search><sort><creationdate>20120301</creationdate><title>Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement</title><author>Yang, XiaoNan ; Zhang, ManHong ; Wang, Yong ; Huo, ZongLiang ; Long, ShiBing ; Zhang, Bo ; Liu, Jing ; Liu, Ming</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c347t-13f333b12a5197dfc17add08c2aeeaca5d7628cfb3bbf7589ffc53e54556ece03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Data storage</topic><topic>Density</topic><topic>Engineering</topic><topic>Memory devices</topic><topic>Oxides</topic><topic>Poisson equation</topic><topic>Schroedinger equation</topic><topic>Threshold voltage</topic><topic>Tunneling</topic><topic>内存</topic><topic>器件</topic><topic>循环过程</topic><topic>电子陷阱</topic><topic>电容</topic><topic>电流测量</topic><topic>纳米</topic><topic>阈值电压</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yang, XiaoNan</creatorcontrib><creatorcontrib>Zhang, ManHong</creatorcontrib><creatorcontrib>Wang, Yong</creatorcontrib><creatorcontrib>Huo, ZongLiang</creatorcontrib><creatorcontrib>Long, ShiBing</creatorcontrib><creatorcontrib>Zhang, Bo</creatorcontrib><creatorcontrib>Liu, Jing</creatorcontrib><creatorcontrib>Liu, Ming</creatorcontrib><collection>中文科技期刊数据库</collection><collection>中文科技期刊数据库-CALIS站点</collection><collection>中文科技期刊数据库-7.0平台</collection><collection>中文科技期刊数据库-工程技术</collection><collection>中文科技期刊数据库- 镜像站点</collection><collection>CrossRef</collection><collection>Engineered Materials Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>Materials Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>Science China. Technological sciences</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Yang, XiaoNan</au><au>Zhang, ManHong</au><au>Wang, Yong</au><au>Huo, ZongLiang</au><au>Long, ShiBing</au><au>Zhang, Bo</au><au>Liu, Jing</au><au>Liu, Ming</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement</atitle><jtitle>Science China. Technological sciences</jtitle><stitle>Sci. China Technol. Sci</stitle><addtitle>SCIENCE CHINA Technological Sciences</addtitle><date>2012-03-01</date><risdate>2012</risdate><volume>55</volume><issue>3</issue><spage>588</spage><epage>593</epage><pages>588-593</pages><issn>1674-7321</issn><eissn>1869-1900</eissn><abstract>The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.</abstract><cop>Heidelberg</cop><pub>SP Science China Press</pub><doi>10.1007/s11431-011-4694-4</doi><tpages>6</tpages></addata></record> |
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| subjects | Data storage Density Engineering Memory devices Oxides Poisson equation Schroedinger equation Threshold voltage Tunneling 内存 器件 循环过程 电子陷阱 电容 电流测量 纳米 阈值电压 |
| title | Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement |
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