Analyzing trap generation in silicon-nanocrystal memory devices using capacitance and current measurement

The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.