Architecture design of high-efficient and non-memory AES crypto-core for WPAN

This paper presents the architecture design of a high‐efficient and non‐memory Advanced Encryption Standard (AES) crypto‐core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (28) to Galois Field GF(((22)2)2) can significantly reduce the hardware complexity of the SubBytes Transformation (S‐box). Besides, the on‐the‐fly key expansion function is used to replace the RAM‐based, and the new on‐the‐fly key scheduler fully supports AES‐128, AES‐192 and AES‐256. Moreover, resource‐sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. FPGA experiment results show that the AES core works at 175.75 MHz clock. It takes about 33 clocks and 66 clocks to complete an AES‐128 encryption and decryption, respectively. That is, the corresponding throughputs are 681.7 and 340.85 Mbps. The hardware cost of the AES design is about 2420 slices with 3‐in‐1 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN chips due to its acceptable power dissipation. Copyright © 2010 John Wiley & Sons, Ltd.