Errors Limiting Split- CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs

The accuracy of the split- CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al 2 O 3 gate dielectric and an InP barrier, through a "simulated experiment" procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on electron devices 2012-04, Vol.59 (4), p.1068-1075
Hauptverfasser: Morassi, L., Verzellesi, G., Han Zhao, Lee, J. C., Veksler, D., Bersuker, G.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The accuracy of the split- CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al 2 O 3 gate dielectric and an InP barrier, through a "simulated experiment" procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I - V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split- CV method can appreciably underestimate the actual channel mobility in these devices, with an error of >;20% and >;50% on peak mobility and high- V GS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing V GS . It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split- CV mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2011.2182513