Exploiting circuit emulation for fast hardness evaluation

Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about...

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Veröffentlicht in:	IEEE transactions on nuclear science 2001-12, Vol.48 (6), p.2210-2216
Hauptverfasser:	Civera, P., Macchiarulo, L., Rebaudengo, M., Reorda, M.S., Violante, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit faults Circuit simulation Circuit testing Circuits Emulation Error analysis Faults Field programmable gate arrays Hardening Hardness Hardware Helium Instruments Integrated circuits Simulation Single event upset Very large scale integration
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Beschreibung
Zusammenfassung:	Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection.
ISSN:	0018-9499 1558-1578
DOI:	10.1109/23.983197