Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

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Veröffentlicht in:IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1738
Hauptverfasser: Osada, K, Shin, Jinuk Luke, Khan, M, Liou, Y, Wang, K, Shoji, K, Kuroda, K, Ikeda, S, Ishibashi, K
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container_end_page
container_issue 11
container_start_page 1738
container_title IEEE journal of solid-state circuits
container_volume 36
creator Osada, K
Shin, Jinuk Luke
Khan, M
Liou, Y
Wang, K
Shoji, K
Kuroda, K
Ikeda, S
Ishibashi, K
description
doi_str_mv 10.1109/4.962296
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title Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
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