A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit
A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We e...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 2002-05, Vol.37 (5), p.599-604 |
|---|---|
| Hauptverfasser: | , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 604 |
|---|---|
| container_issue | 5 |
| container_start_page | 599 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 37 |
| creator | Yamaoka, M. Yanagisawa, K. Shukuri, S. Norisue, K. Ishibashi, K. |
| description | A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor. |
| doi_str_mv | 10.1109/4.997853 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_992874975</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>997853</ieee_id><sourcerecordid>2629238401</sourcerecordid><originalsourceid>FETCH-LOGICAL-c365t-51a97c52af96da0b39be33afb1c7fc74cbe6bf43990425c1c241b2361baa680d3</originalsourceid><addsrcrecordid>eNqF0c1LwzAUAPAgCs4pePYUPOg8dCZN0jTHMfwYDDyo4K2k6euW0Y-ZtEL_e7t1ePCgp8fj_fLeCw-hS0qmlBJ1z6dKyViwIzSiQsQBlezjGI0IoXGgQkJO0Zn3mz7lPKYjVM6w73wDJV6-LnAJZe067CBrq0xXpsMNmHVlP1vArbfVCusKWwjyQvs1ntjqC5yHYKUbCKAA07g6A7yv3uGtq1dOl-XumbHOtLY5Rye5LjxcHOIYvT8-vM2fg-XL02I-WwaGRaIJBNVKGhHqXEWZJilTKTCm85QamRvJTQpRmnOmFOGhMNSEnKYhi2iqdRSTjI3R7dC336Hf3TdJab2BotAV1K1PFJGKC6JEL2_-lGEccU4k-R9KyVW8h9e_4KZuXdV_N1EqjHsld2MnAzKu9t5BnmydLbXrEkqS3R0Tngx37OnVQC0A_LBD8Rti75g8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>992874975</pqid></control><display><type>article</type><title>A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit</title><source>IEEE Electronic Library (IEL)</source><creator>Yamaoka, M. ; Yanagisawa, K. ; Shukuri, S. ; Norisue, K. ; Ishibashi, K.</creator><creatorcontrib>Yamaoka, M. ; Yanagisawa, K. ; Shukuri, S. ; Norisue, K. ; Ishibashi, K.</creatorcontrib><description>A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.997853</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Cache memory ; Circuit testing ; Circuits ; CMOS ; CMOS logic circuits ; CMOS process ; Fatigue tests ; Flash memory (computers) ; Large scale integration ; Logic ; Logic testing ; Microprocessors ; Programming ; Reduced instruction set computing ; Redundancy ; System testing</subject><ispartof>IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.599-604</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2002</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-51a97c52af96da0b39be33afb1c7fc74cbe6bf43990425c1c241b2361baa680d3</citedby><cites>FETCH-LOGICAL-c365t-51a97c52af96da0b39be33afb1c7fc74cbe6bf43990425c1c241b2361baa680d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/997853$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/997853$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yamaoka, M.</creatorcontrib><creatorcontrib>Yanagisawa, K.</creatorcontrib><creatorcontrib>Shukuri, S.</creatorcontrib><creatorcontrib>Norisue, K.</creatorcontrib><creatorcontrib>Ishibashi, K.</creatorcontrib><title>A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.</description><subject>Cache memory</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS logic circuits</subject><subject>CMOS process</subject><subject>Fatigue tests</subject><subject>Flash memory (computers)</subject><subject>Large scale integration</subject><subject>Logic</subject><subject>Logic testing</subject><subject>Microprocessors</subject><subject>Programming</subject><subject>Reduced instruction set computing</subject><subject>Redundancy</subject><subject>System testing</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0c1LwzAUAPAgCs4pePYUPOg8dCZN0jTHMfwYDDyo4K2k6euW0Y-ZtEL_e7t1ePCgp8fj_fLeCw-hS0qmlBJ1z6dKyViwIzSiQsQBlezjGI0IoXGgQkJO0Zn3mz7lPKYjVM6w73wDJV6-LnAJZe067CBrq0xXpsMNmHVlP1vArbfVCusKWwjyQvs1ntjqC5yHYKUbCKAA07g6A7yv3uGtq1dOl-XumbHOtLY5Rye5LjxcHOIYvT8-vM2fg-XL02I-WwaGRaIJBNVKGhHqXEWZJilTKTCm85QamRvJTQpRmnOmFOGhMNSEnKYhi2iqdRSTjI3R7dC336Hf3TdJab2BotAV1K1PFJGKC6JEL2_-lGEccU4k-R9KyVW8h9e_4KZuXdV_N1EqjHsld2MnAzKu9t5BnmydLbXrEkqS3R0Tngx37OnVQC0A_LBD8Rti75g8</recordid><startdate>20020501</startdate><enddate>20020501</enddate><creator>Yamaoka, M.</creator><creator>Yanagisawa, K.</creator><creator>Shukuri, S.</creator><creator>Norisue, K.</creator><creator>Ishibashi, K.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20020501</creationdate><title>A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit</title><author>Yamaoka, M. ; Yanagisawa, K. ; Shukuri, S. ; Norisue, K. ; Ishibashi, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c365t-51a97c52af96da0b39be33afb1c7fc74cbe6bf43990425c1c241b2361baa680d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Cache memory</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS logic circuits</topic><topic>CMOS process</topic><topic>Fatigue tests</topic><topic>Flash memory (computers)</topic><topic>Large scale integration</topic><topic>Logic</topic><topic>Logic testing</topic><topic>Microprocessors</topic><topic>Programming</topic><topic>Reduced instruction set computing</topic><topic>Redundancy</topic><topic>System testing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yamaoka, M.</creatorcontrib><creatorcontrib>Yanagisawa, K.</creatorcontrib><creatorcontrib>Shukuri, S.</creatorcontrib><creatorcontrib>Norisue, K.</creatorcontrib><creatorcontrib>Ishibashi, K.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamaoka, M.</au><au>Yanagisawa, K.</au><au>Shukuri, S.</au><au>Norisue, K.</au><au>Ishibashi, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2002-05-01</date><risdate>2002</risdate><volume>37</volume><issue>5</issue><spage>599</spage><epage>604</epage><pages>599-604</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/4.997853</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.599-604 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_journals_992874975 |
| source | IEEE Electronic Library (IEL) |
| subjects | Cache memory Circuit testing Circuits CMOS CMOS logic circuits CMOS process Fatigue tests Flash memory (computers) Large scale integration Logic Logic testing Microprocessors Programming Reduced instruction set computing Redundancy System testing |
| title | A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T10%3A28%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20system%20LSI%20memory%20redundancy%20technique%20using%20an%20ie-flash%20(inverse-gate-electrode%20flash)%20programming%20circuit&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Yamaoka,%20M.&rft.date=2002-05-01&rft.volume=37&rft.issue=5&rft.spage=599&rft.epage=604&rft.pages=599-604&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.997853&rft_dat=%3Cproquest_RIE%3E2629238401%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=992874975&rft_id=info:pmid/&rft_ieee_id=997853&rfr_iscdi=true |