A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We e...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 2002-05, Vol.37 (5), p.599-604
Hauptverfasser: Yamaoka, M., Yanagisawa, K., Shukuri, S., Norisue, K., Ishibashi, K.
Format: Artikel
Sprache:eng
Schlagworte:
Cache memory
Circuit testing
Circuits
CMOS
CMOS logic circuits
CMOS process
Fatigue tests
Flash memory (computers)
Large scale integration
Logic
Logic testing
Microprocessors
Programming
Reduced instruction set computing
Redundancy
System testing
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.997853