The CMOS carry-forward adders

The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-/spl mu/m CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm/sup 2/ silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps.