FPGA Implementation of a Real-Time NARMA-Based Digital Adaptive Predistorter

This paper presents the design of a nonlinear autoregressive moving average (NARMA) digital adaptive predistorter (DAPD) for power amplifier (PA) linearization consisting of a low-complex closed-loop architecture. Both the predistortion function and the adaptation algorithm are fully implemented in a field-programmable gate array (FPGA) device, without the need for using any additional coprocessor. The proposed predistortion architecture is capable to compensate for both the PA nonlinear distortion and memory effects. Moreover, this DAPD allows almost real-time adaptation without interrupting the normal transmission. The computational complexity introduced by this DAPD is studied in this paper. The proposed theoretical design is implemented in an FPGA, whereas the linearization performance of the DAPD is validated through simulated and experimental results.