Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs
CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. Th...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2011-12, Vol.58 (6), p.2761-2767 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Chatterjee, I. Narasimham, B. Mahatme, N. N. Bhuva, B. L. Schrimpf, R. D. Wang, J. K. Bartz, B. Pitta, E. Buer, M. |
| description | CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This paper presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the "Single Event Upset Reversal" mechanism that reduces sensitivity at higher LETs. |
| doi_str_mv | 10.1109/TNS.2011.2172817 |
| format | Article |
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| subjects | Charge CMOS CMOS technology Collection Confinement Dual-well Electric charge MOSFETs multiple-node charge collection Particle energy pulse quenching Radiation effects reinforcing charge collection Single event upset Single event upsets single-vent upset reversal soft error SRAM SRAM chips triple-well |
| title | Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs |
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