A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area,...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2012-01, Vol.20 (1), p.126-134
Hauptverfasser: Geng-Ming Chiu, Li, James Chien-Mo
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Boundaries
Compatibility
Computer hacking
Computer information security
Design engineering
Design for testability
Discrete Fourier transforms
Electronics
Encryption
Exact sciences and technology
Flip-flops
IP networks
Keys
Registers
scan
security
System-on-a-chip
Testing, measurement, noise and reliability
Very large scale integration
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Beschreibung
Zusammenfassung:This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2089071