Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below
Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and co...
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Veröffentlicht in: | IEEE transactions on semiconductor manufacturing 2008-02, Vol.21 (1), p.46-54 |
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description | Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography. |
doi_str_mv | 10.1109/TSM.2007.913191 |
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Characterizing Standard Cell Behavior at 90 nm and Below</title><source>IEEE Electronic Library (IEL)</source><creator>Aitken, R.C.</creator><creatorcontrib>Aitken, R.C.</creatorcontrib><description>Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. 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Solid state devices</subject><subject>Semiconductors</subject><subject>standard cells</subject><subject>Threshold voltage</subject><subject>Transistors</subject><subject>variation</subject><issn>0894-6507</issn><issn>1558-2345</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkb1vFDEQxS0UJC6BmoLGQgpUexl_2xWCC19SThQXaC2fd5Y42ttN7D2i8NfHp4tSpEiqkfx-bzTPj5C3DOaMgTs5Xy3nHMDMHRPMsRdkxpSyDRdSHZAZWCcbrcC8IoelXAIwKZ2ZkeUpdhgnOmb6J-QUpjQOn-jiIuQQJ8zpfxr-0tUUhjbkli6w7-kXvAj_UjWEiTqgw4ZWtb72481r8rILfcE39_OI_P729Xzxozn79f3n4vNZEyUTU9Ma1UKHyoLgWnOrWxdg3SKY1lgTndPaxOAMaxmrqlWaC7M2sOZyjRFRHJGP-71XebzeYpn8JpVYjwsDjtviHQjNldXyWdIaBcrWr6jkhydJISWzWuzA94_Ay3Gbh5rXO8Z5TeBchU72UMxjKRk7f5XTJuRbz8Dv-vK1L7_ry-_7qo7j-7WhxNB3OQwxlQdbRZVhdpfo3Z5LiPggSykNd1rcAVlcmok</recordid><startdate>20080201</startdate><enddate>20080201</enddate><creator>Aitken, R.C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Semiconductors</topic><topic>standard cells</topic><topic>Threshold voltage</topic><topic>Transistors</topic><topic>variation</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Aitken, R.C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on semiconductor manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aitken, R.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below</atitle><jtitle>IEEE transactions on semiconductor manufacturing</jtitle><stitle>TSM</stitle><date>2008-02-01</date><risdate>2008</risdate><volume>21</volume><issue>1</issue><spage>46</spage><epage>54</epage><pages>46-54</pages><issn>0894-6507</issn><eissn>1558-2345</eissn><coden>ITSMED</coden><abstract>Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TSM.2007.913191</doi><tpages>9</tpages></addata></record> |
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subjects | Applied sciences Characterization Circuit faults Circuit testing Continuums defect modeling Defects Delay Design for testability design margin Electronics Exact sciences and technology Geometry History Leakage Lithography Manufacturing Microelectronic fabrication (materials and surfaces technology) Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors standard cells Threshold voltage Transistors variation |
title | Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below |
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