A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring
A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-/spl mu/m CMOS....
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Veröffentlicht in: | IEEE journal of solid-state circuits 2006-02, Vol.41 (2), p.483-495 |
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Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-/spl mu/m CMOS. It performs 8-point to 4096-point complex FFT/IFFT with power-consumption scalability and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2005.862344 |