[Formula Omitted] Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor
The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.
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| Veröffentlicht in: | IEEE electron device letters 2009-12, Vol.30 (12), p.1323 |
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| container_issue | 12 |
| container_start_page | 1323 |
| container_title | IEEE electron device letters |
| container_volume | 30 |
| creator | Jhon, Hee-Sauk Lee, Jae-Hong Lee, Jaeho Oh, Byoungchan Song, Ickhyun Yun, Yeonam Park, Byung-Gook Lee, Jong-Duk Shin, Hyungcheol |
| description | The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines. |
| doi_str_mv | 10.1109/LED.2009.2032249 |
| format | Article |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 2009-12, Vol.30 (12), p.1323 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_proquest_journals_912021767 |
| source | IEEE Electronic Library (IEL) |
| title | [Formula Omitted] Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor |
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