[Formula Omitted] Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

[Formula Omitted] Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.

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Veröffentlicht in:IEEE electron device letters 2009-12, Vol.30 (12), p.1323
Hauptverfasser: Jhon, Hee-Sauk, Lee, Jae-Hong, Lee, Jaeho, Oh, Byoungchan, Song, Ickhyun, Yun, Yeonam, Park, Byung-Gook, Lee, Jong-Duk, Shin, Hyungcheol
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Sprache:eng
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Zusammenfassung:The proposed layout exhibits the improvement of f max up to ~ 21% without fT variation compared to a reference device due to reduced extrinsic Rg and C gd parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2009.2032249