Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to...

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Veröffentlicht in:	IEEE transactions on nuclear science 2009-12, Vol.56 (6), p.3050-3056
Hauptverfasser:	Ahlbin, J.R., Massengill, L.W., Bhuva, B.L., Narasimham, B., Gadlage, M.J., Eaton, P.H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Charge Charge sharing Circuits CMOS CMOS logic circuits CMOS technology Collection Constraining Logic gates Logic testing Mathematical models Microelectronics Pulse amplifiers Pulse circuits pulse quenching Pulse width Quenching single-event single-event transient single-event upset Space vector pulse width modulation Transistors Voltage
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Zusammenfassung:	Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or ¿quench,¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.
ISSN:	0018-9499 1558-1578
DOI:	10.1109/TNS.2009.2033689