An Efficient SER Estimation Method for Combinational Circuits

Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation, and charged particles. These phenomena, also known as single-event upsets (SEU), induce current pulses at random times and random locations in a digital circuit. In this article, we...

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Veröffentlicht in:	IEEE transactions on reliability 2011-12, Vol.60 (4), p.742-747
Hauptverfasser:	Kehl, N., Rosenstiel, W.
Format:	Artikel
Sprache:	eng
Schlagworte:	Combinational circuits Combinational logic circuits Error analysis Integrated circuit modeling integrated-circuit Logic gates Semiconductor device modeling Single event transient Single event upset soft error soft error rate Transient analysis
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