A software solution for chip rate processing in CDMA wireless infrastructure

A software solution for chip rate processing in CDMA wireless infrastructure

Third-generation cellular infrastructure requires extremely high-performance signal processing in the baseband receiver. Currently, chip rate processing is implemented using FPGA and ASIC technology. The use of a digital signal processor is explored for UTRA FDD systems with the goal of reducing cos...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE communications magazine 2002-02, Vol.40 (2), p.163-167
Hauptverfasser: Lange, K., Blanke, G., Rifaat, R.
Format: Magazinearticle
Sprache:eng
Schlagworte:
3G mobile communication
Base stations
Baseband
Chips
Computer architecture
Cost engineering
Costs
Flexibility
Frequency
History
Infrastructure
Land mobile radio
Microprocessors
Multiaccess communication
Platforms
Receivers
Signal processing
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Third-generation cellular infrastructure requires extremely high-performance signal processing in the baseband receiver. Currently, chip rate processing is implemented using FPGA and ASIC technology. The use of a digital signal processor is explored for UTRA FDD systems with the goal of reducing cost and increasing flexibility. By combining chip rate and symbol rate processing within a single platform and taking advantage of the natural capacity of the air interface, load balancing can be performed, which reduces the amount of processing power needed, thereby reducing the cost of the receiver.
ISSN:0163-6804
1558-1896
DOI:10.1109/35.983924