Programmable interleaver design for analog iterative decoders

Programmable interleaver design for analog iterative decoders

Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are ofte...

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Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2002-07, Vol.49 (7), p.457-464
Hauptverfasser: Gaudet, V.C., Gaudet, R.J., Gulak, P.G.
Format: Artikel
Sprache:eng
Schlagworte:
Capacitance
Circuits
Delay
Iterative algorithms
Iterative decoding
Logic programming
Random access memory
Silicon
Switches
Turbo codes
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Zusammenfassung:Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of 100, as opposed to full crossbars, while maintaining full programmability.
ISSN:1057-7130
1558-125X
DOI:10.1109/TCSII.2002.805022