Parasitics extraction with multipole refinement
Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today's integrated systems, however, makes fast analysis crucial as well. We present a novel...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2004-02, Vol.23 (2), p.288-292 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 23 |
| creator | Beattie, M.W. Pileggi, L.T. |
| description | Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today's integrated systems, however, makes fast analysis crucial as well. We present a novel hierarchical potential evaluation technique which is able to represent detailed near-field and global far-field couplings with equal accuracy and efficiency by combining the best features of known hierarchical approaches in this field. |
| doi_str_mv | 10.1109/TCAD.2003.822109 |
| format | Article |
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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2004-02, Vol.23 (2), p.288-292 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_proquest_journals_883898493 |
| source | IEEE Electronic Library (IEL) |
| subjects | Capacitance Chip scale packaging Chips (electronics) Computer aided design Conductors Couplings Delay Design engineering Extraction Inductance Integrated circuits Logic Mathematical models Multipoles Performance analysis Predictive models Two dimensional displays Wiring |
| title | Parasitics extraction with multipole refinement |
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