Embedded test control schemes using iBIST for SOCs

Embedded test control schemes using iBIST for SOCs

This paper presents novel control schemes for testing embedded cores in a system-on-a-chip. It converts a traditional built-in self-test (BIST) scheme into an externally controllable scheme to achieve high test quality within optimal test execution time without inserting test points. Interactive BIS...

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Veröffentlicht in:IEEE transactions on instrumentation and measurement 2005-06, Vol.54 (3), p.956-964
Hauptverfasser: Kay, D., Sung Chung, Mourad, S.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
Automatic testing
Bandwidth
Built-in self-test
built-in self-test (BIST)
Circuit faults
Circuit testing
Control systems
Costs
data compression
design
Design engineering
Embedded test
experimentation
Fault detection
Instrumentation
Interactive
Optimization
Simulation
System on chip
System testing
System-on-a-chip
Test pattern generators
test resource allocation
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Beschreibung
Zusammenfassung:This paper presents novel control schemes for testing embedded cores in a system-on-a-chip. It converts a traditional built-in self-test (BIST) scheme into an externally controllable scheme to achieve high test quality within optimal test execution time without inserting test points. Interactive BIST promotes design and test reuse without revealing IP information by using a pattern matching technique instead of fault simulation.
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2005.847349