Programmable nanowire circuits for nanoprocessors

Programmable nanowire nanoprocessor In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, Yan et al . demonstrate scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting of 496 configurable transistor nodes in an area of about 960 square micrometres, can be programmed and operated as a full-adder or full-subtractor circuit, and used for various other functions including multiplexers. It should be possible in future to cascade these logic tiles to realize fully integrated nanoprocessors with computing, memory and addressing capabilities. In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, this study demonstrates scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting 496 configurable transistor nodes in an area of about 960 μm 2 , could be programmed and operated as, among other functions, a full-adder, full-subtractor and multiplexer. The promise is that these logic tiles can be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities. A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up 1 , 2 , 3 . Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes 1 , 4 , 5 , 6 , 7 , 8 , but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array 9 , although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor 10 , 11 owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires 12 coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmabl