Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks

The field of embedded network security has seen increasing interest in developing lightweight and efficient chaotic map-based key exchange protocols. Due to their semi-group feature, Chebyshev polynomials are widely used in various protocols to produce a shared key between two parties. However, the lack of efficient and secure methods for computing high-degree polynomials has significantly restricted their practical use in real-world embedded applications. This work aims to develop a fast and reliable algorithm for computing Chebyshev polynomials and proposes a reconfigurable FPGA-based architecture for its implementation. Additionally, the proposed hardware architecture is utilized to deploy a key exchange protocol based on Chebyshev polynomials within a TCP server-client network platform. Security analysis demonstrates that the proposed hardware implementation is robust against power analysis attacks. For a 256-bit field size, the architecture uses 3.9k slices on the Zynq-ZC702 and 4k slices on the Kintex-7, without employing any hardware accelerators such as DSP and BRAM. It achieves Chebyshev polynomial computation in 1.94 ms and 1.03 ms, respectively. This design outperforms existing lightweight key exchange protocols in terms of area-time products, making it an adequate alternative for resource-constrained embedded systems.