Toward monolithic growth integration of nanowire electronics in 3D architecture: a review

Quasi-one-dimensional (1D) semiconducting nanowires (NWs), with excellent electrostatic control capability, are widely regarded as advantageous channels for the fabrication of high-performance microelectronics, memories, and sensors. For example, the latest Si field-effect-transistor (FET) technology nodes, < N5 nm, use horizontally-stacked SiNWs or nanosheet channels in a gate-all-around (GAA) configuration. However, further scaling of the top-down etching fabrication is reaching physical limits, necessitating the development of new fabrication or integration technologies in monolithic three dimensional (3D) architecture to push Moore’s law forward. These new capabilities are also critical, for implementing of more advanced non von Neumann paradigms of in-memory and neuromorphic computing. For this, a versatile and highly controllable low-temperature growth integration of orderly 1D SiNW channels is desired, as it will provide an alternative or complementary new route to fabricate a multilayer of Si CMOS logics/memories in a fully 3D stacked manner. In this study, we assess the evolution and recent progress of catalytic growth strategies for ultrathin 1D channels in-plane or planar NWs, and revisit the key mechanisms and technological milestones in geometry, lattice quality, line-shape, position, and composition controls. We aim to eventually establish a reliable catalytic growth integration strategy, suitable for the fabrication of GAA FETs and the implementation of a monolithic 3D integration architecture. Finally, we also present a summary and perspectives on the current challenges and future opportunities of monolithic growth integration of NW electronics in 3D architecture.