Development of a Model for Prediction of IoT Processor Power Utilization Using Instruction Dissection-Based Technique

The global drive towards a net-zero world and commitments from advanced countries towards a significant cut of greenhouse gases by 2030 are objectives that have compelled a new technological paradigm that must align with new global initiatives towards meeting agreed objectives towards the net-zero w...

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Veröffentlicht in:IEEE access 2024, Vol.12, p.164682-164699
Hauptverfasser: Yusuf, Dibal P., Ahmed, Hashim E., Onwuka, Elizabeth N., Suleiman, Zubair
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Sprache:eng
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Zusammenfassung:The global drive towards a net-zero world and commitments from advanced countries towards a significant cut of greenhouse gases by 2030 are objectives that have compelled a new technological paradigm that must align with new global initiatives towards meeting agreed objectives towards the net-zero world. The Internet-of-Things (IoT) is a technology that has shown strong viability in assisting nations and corporations in meeting global commitments to the net-zero goal. To be effective, the operation of IoT devices must meet very tight constraints; consequently, the design of the electronics, and applications that run on IoT devices must be optimal especially in power utilization considerations. It is in this regard that this paper presents the design of a power prediction model for a Cortex M processor. The design was achieved through a unique methodology in which an instruction dissector played a central role in determining the exact instructions that were executed, rather than using a generalized set of instructions from an instruction grouping. Multivariate Adaptive Regression Splines (MARS) was used as the machine learning technique for deriving the prediction models. A key feature of using MARS is that the predictor variables having the greatest effect on the models were identified as the MVN and SBC instructions. A performance comparison of the design in this paper was made with similar designs where it was shown that the approach of the design in this work yielded more robust models with a reported error rate of 0.000629193 for logic power and 0.023096787 for data power.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2024.3491632