Design of an automatic gain control loop for high speed communication

This paper presents the design of an automatic gain control (AGC) loop for high‐speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell‐based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier‐based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW. An automatic gain control (AGC) loop for high‐speed communication systems has been proposed. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1–30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design.