A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

This paper presents an NMOS low dropout (LDO) regulator with a high-power supply rejection ratio (PSRR) and low quiescent current that uses an intrinsic gain-tracking ripple cancellation (IGTRC) technique with an adaptive biasing scheme. The proposed LDO is fabricated using a 180 nm CMOS process and...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-11, Vol.71 (11), p.4951-4960
Hauptverfasser: Kim, Jung Sik, Ha, Seunggyun, Jeong, Hongyup, Roh, Jeongjin
Format: Artikel
Sprache:eng
Schlagworte:
Gain
high power supply rejection ratio (PSRR)
Intrinsic gain-tracking ripple cancellation (IGTRC)
Logic gates
loop-gain stabilization
low drop-out regulator (LDO)
low quiescent current
Mathematical models
Metal oxide semiconductors
MOS devices
Regulators
Resistors
Tracking
Transistors
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Beschreibung
Zusammenfassung:This paper presents an NMOS low dropout (LDO) regulator with a high-power supply rejection ratio (PSRR) and low quiescent current that uses an intrinsic gain-tracking ripple cancellation (IGTRC) technique with an adaptive biasing scheme. The proposed LDO is fabricated using a 180 nm CMOS process and achieves a quiescent current of 3.7~\mu A with superior figure-of-merits (FOMs) of 7.6E9 (FOM1) and 0.005 ps (FOM2).
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2024.3422001