A Single-Ended Inverter-Based Addition-Only Feed-Forward Equalization Transmitter

This article presents an inverter-based four-tap addition-only feed-forward equalizing (A-FFE) transmitter (TX) for compact and power-efficient single-ended interfaces. Source-series terminated (SST) drivers are widely used in conventional FFE (C-FFE) TXs. However, linear resistors in C-FFE SST TXs occupy too much area and add significant parasitic capacitance, degrading power efficiency, and output bandwidth. To overcome these problems, we propose a new feed-forward equalization (FFE) architecture dubbed A-FFE that completely eliminates subtractions between FFE taps and improves the robustness to quantization errors of coefficients. These advantages of the proposed architecture allow to utilize area-and-power-efficient inverter drivers in FFE. An inverter-based four-tap A-FFE TX was designed and fabricated in a 28-nm CMOS process. The TX achieved a data rate of 20 Gb/s/pin, an eye height of 55.1 mV, and an eye width of 0.44 UI with a 15-dB PCB trace, while consuming 1.18 pJ/b and achieving the worst eye sensitivity of 68%. The eye-opening was decreased only by 13.6%, when the most sensitive FFE coefficient was reduced by 20%. Because it uses area-efficient inverter drivers without resistors, the TX occupies only 1149~{\mu } m2.