Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language

Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language

A combination of features borrowed from Carry Look-Ahead adders (CLAs) and Novel Carry Increment adders (CIAs) improved the adder’s simplicity and performance. The size and speed of the high-speed adder were reduced by twenty samples. Both the Carry Look-Ahead adder (CLA) and the Novel Carry Increme...

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Hauptverfasser: Mohithsaicharan, Karanam, Jagadeesh, P.
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High speed
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description A combination of features borrowed from Carry Look-Ahead adders (CLAs) and Novel Carry Increment adders (CIAs) improved the adder’s simplicity and performance. The size and speed of the high-speed adder were reduced by twenty samples. Both the Carry Look-Ahead adder (CLA) and the Novel Carry Increment adder (CIA) utilise 10 samples, however the CIA is quicker and requires less space (p
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fullrecord <record><control><sourceid>proquest_scita</sourceid><recordid>TN_cdi_proquest_journals_3104168416</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>3104168416</sourcerecordid><originalsourceid>FETCH-LOGICAL-p631-616900e019c9b88da68fe70e41fc30ddb194b33a1ed329b3c5a2c18282632e93</originalsourceid><addsrcrecordid>eNotUFFLwzAYDKLgnD74DwK-CZ35kjZNHmU6JwwEFfEtpEm6ZXbpTFpl_97K-nDcwx3H3SF0DWQGhLO7YkYoFSDhBE2gKCArOfBTNCFE5hnN2ec5ukhpSwiVZSkmSL32ofM7h3XQzSH5hNsah_bHNdjoGA_YBxPdzoUOa2tdxL--24xS07Zfmd44bUetTz6s8cfyYYUbHda9XrtLdFbrJrmrkafobfH4Pl9mq5en5_n9KttzBtnQURLiCEgjKyGs5qJ2JXE51IYRayuQecWYBmcZlRUzhaYGBBWUM-okm6KbY-o-tt-9S53atn0cFiXFgOTAxYDBdXt0JeM73fk2qH30Ox0PCoj6v08VaryP_QG5YWFE</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>3104168416</pqid></control><display><type>conference_proceeding</type><title>Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language</title><source>AIP Journals Complete</source><creator>Mohithsaicharan, Karanam ; Jagadeesh, P.</creator><contributor>Prabu, R. Thandaiah ; Ramkumar, G. ; G, Anitha ; Vidhyalakshmi, S.</contributor><creatorcontrib>Mohithsaicharan, Karanam ; Jagadeesh, P. ; Prabu, R. Thandaiah ; Ramkumar, G. ; G, Anitha ; Vidhyalakshmi, S.</creatorcontrib><description>A combination of features borrowed from Carry Look-Ahead adders (CLAs) and Novel Carry Increment adders (CIAs) improved the adder’s simplicity and performance. The size and speed of the high-speed adder were reduced by twenty samples. Both the Carry Look-Ahead adder (CLA) and the Novel Carry Increment adder (CIA) utilise 10 samples, however the CIA is quicker and requires less space (p&lt;0.045). As a conclusion, one high-speed adder design is superior to the other, and that is the Novel Carry Increment adder (CIA). The time and space are both improved substantially by Carry Look-Ahead (CLA) designs.</description><identifier>ISSN: 0094-243X</identifier><identifier>EISSN: 1551-7616</identifier><identifier>DOI: 10.1063/5.0228191</identifier><identifier>CODEN: APCPCS</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>High speed</subject><ispartof>AIP conference proceedings, 2024, Vol.2871 (1)</ispartof><rights>Author(s)</rights><rights>2024 Author(s). Published under an exclusive license by AIP Publishing.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/acp/article-lookup/doi/10.1063/5.0228191$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,790,4497,23910,23911,25119,27903,27904,76130</link.rule.ids></links><search><contributor>Prabu, R. Thandaiah</contributor><contributor>Ramkumar, G.</contributor><contributor>G, Anitha</contributor><contributor>Vidhyalakshmi, S.</contributor><creatorcontrib>Mohithsaicharan, Karanam</creatorcontrib><creatorcontrib>Jagadeesh, P.</creatorcontrib><title>Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language</title><title>AIP conference proceedings</title><description>A combination of features borrowed from Carry Look-Ahead adders (CLAs) and Novel Carry Increment adders (CIAs) improved the adder’s simplicity and performance. The size and speed of the high-speed adder were reduced by twenty samples. Both the Carry Look-Ahead adder (CLA) and the Novel Carry Increment adder (CIA) utilise 10 samples, however the CIA is quicker and requires less space (p&lt;0.045). As a conclusion, one high-speed adder design is superior to the other, and that is the Novel Carry Increment adder (CIA). The time and space are both improved substantially by Carry Look-Ahead (CLA) designs.</description><subject>High speed</subject><issn>0094-243X</issn><issn>1551-7616</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2024</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNotUFFLwzAYDKLgnD74DwK-CZ35kjZNHmU6JwwEFfEtpEm6ZXbpTFpl_97K-nDcwx3H3SF0DWQGhLO7YkYoFSDhBE2gKCArOfBTNCFE5hnN2ec5ukhpSwiVZSkmSL32ofM7h3XQzSH5hNsah_bHNdjoGA_YBxPdzoUOa2tdxL--24xS07Zfmd44bUetTz6s8cfyYYUbHda9XrtLdFbrJrmrkafobfH4Pl9mq5en5_n9KttzBtnQURLiCEgjKyGs5qJ2JXE51IYRayuQecWYBmcZlRUzhaYGBBWUM-okm6KbY-o-tt-9S53atn0cFiXFgOTAxYDBdXt0JeM73fk2qH30Ox0PCoj6v08VaryP_QG5YWFE</recordid><startdate>20240913</startdate><enddate>20240913</enddate><creator>Mohithsaicharan, Karanam</creator><creator>Jagadeesh, P.</creator><general>American Institute of Physics</general><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope></search><sort><creationdate>20240913</creationdate><title>Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language</title><author>Mohithsaicharan, Karanam ; Jagadeesh, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p631-616900e019c9b88da68fe70e41fc30ddb194b33a1ed329b3c5a2c18282632e93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2024</creationdate><topic>High speed</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mohithsaicharan, Karanam</creatorcontrib><creatorcontrib>Jagadeesh, P.</creatorcontrib><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Mohithsaicharan, Karanam</au><au>Jagadeesh, P.</au><au>Prabu, R. Thandaiah</au><au>Ramkumar, G.</au><au>G, Anitha</au><au>Vidhyalakshmi, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language</atitle><btitle>AIP conference proceedings</btitle><date>2024-09-13</date><risdate>2024</risdate><volume>2871</volume><issue>1</issue><issn>0094-243X</issn><eissn>1551-7616</eissn><coden>APCPCS</coden><abstract>A combination of features borrowed from Carry Look-Ahead adders (CLAs) and Novel Carry Increment adders (CIAs) improved the adder’s simplicity and performance. The size and speed of the high-speed adder were reduced by twenty samples. Both the Carry Look-Ahead adder (CLA) and the Novel Carry Increment adder (CIA) utilise 10 samples, however the CIA is quicker and requires less space (p&lt;0.045). As a conclusion, one high-speed adder design is superior to the other, and that is the Novel Carry Increment adder (CIA). The time and space are both improved substantially by Carry Look-Ahead (CLA) designs.</abstract><cop>Melville</cop><pub>American Institute of Physics</pub><doi>10.1063/5.0228191</doi><tpages>7</tpages></addata></record>
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subjects High speed
title Runtime analysis of novel carry increment adder with carry look-ahead adder using VHDL language
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T03%3A57%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_scita&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Runtime%20analysis%20of%20novel%20carry%20increment%20adder%20with%20carry%20look-ahead%20adder%20using%20VHDL%20language&rft.btitle=AIP%20conference%20proceedings&rft.au=Mohithsaicharan,%20Karanam&rft.date=2024-09-13&rft.volume=2871&rft.issue=1&rft.issn=0094-243X&rft.eissn=1551-7616&rft.coden=APCPCS&rft_id=info:doi/10.1063/5.0228191&rft_dat=%3Cproquest_scita%3E3104168416%3C/proquest_scita%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=3104168416&rft_id=info:pmid/&rfr_iscdi=true