A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

This brief presents a 48-Gb/s quarter-rate four-level pulse amplitude modulation (PAM-4) receiver with a baud-rate clock and data recovery circuit. The modified time-interpolated latch (MTIL) is proposed to reduce the number of input comparators. The offset voltages of the comparators and the inters...

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Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-09, Vol.71 (9), p.4156-4160
Hauptverfasser: Huang, Yuan-Pang, Liu, Shen-Iuan
Format: Artikel
Sprache:eng
Schlagworte:
Bit error rate
CDR circuits
Circuits
clock and data recovery
Clock recovery
Clocks
Comparators
continuous-time linear equalizer
Data recovery
Delays
DH-HEMTs
Four-level pulse amplitude modulation
Latches
phase detector
Pulse amplitude modulation
Receivers
Threshold voltage
time-interpolated latch
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Beschreibung
Zusammenfassung:This brief presents a 48-Gb/s quarter-rate four-level pulse amplitude modulation (PAM-4) receiver with a baud-rate clock and data recovery circuit. The modified time-interpolated latch (MTIL) is proposed to reduce the number of input comparators. The offset voltages of the comparators and the intersecting voltages of the MTILs are calibrated by using the foreground calibration. This PAM-4 receiver is fabricated in a 40-nm CMOS process and the active area is 0.089mm2. The power consumption is 62.8mW and the calculated energy efficiency is 1.31pJ/b. For a PRBS of 27-1, the bit-error rate is less than 10−12.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2024.3390653