PLL architecture with a composite PFD and variable loop filter

A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when $\Delta \phi \...

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Veröffentlicht in:	IET circuits, devices & systems devices & systems, 2018-05, Vol.12 (3), p.256-262
Hauptverfasser:	K.K, Abdul Majeed, Kailath, Binsu J
Format:	Artikel
Sprache:	eng
Schlagworte:	Boolean charge pump charge pump circuits Charge pumps circuit stability CMOS CMOS analogue integrated circuits complementary metal-oxide-semiconductor process composite PFD Design frequency 100 kHz frequency 2.56 GHz frequency measurement Logic phase detectors phase frequency detector Phase locked loops phase margin equalization phase measurement Phase noise phase-locked loop architecture PLL architecture Research Article size 180 nm stability time 2.05 mus time 3.412 ps Topology Tracking Transistors UHF detectors UHF filters UHF integrated circuits UHF measurement UHF oscillators variable loop filter topology voltage-controlled oscillator voltage-controlled oscillators
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Beschreibung
Zusammenfassung:	A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when $\Delta \phi \gt \pi $Δϕ>π and provides a lower-gain and loop BW during tracking when $\Delta \phi \lt \pi $Δϕ
ISSN:	1751-858X 1751-8598 1751-8598
DOI:	10.1049/iet-cds.2017.0336