SEE Failure Analysis of Hi-rel ASIC for Spacecraft Applications

Miniaturized electronic devices are essential to improve the performance, reduce the weight and volume, and improve reliability of electronic packages in a spacecraft. With technology scaling, a prime reliability challenge for CMOS devices used in spacecrafts is the occurrence of soft errors due to the propagation of SETs in the space radiation environment. ASICs undergo stringent quality tests to ensure reliable operation of the spacecraft during its mission life. In general, SEE tolerance qualification tests estimate the heavy ion radiation tolerance of CMOS devices for space application. A new SEE test methodology using available scan structure in digital ASICs is proposed. Here, different patterns are loaded in the scan chain which helps to differentiate between SET and SEU soft errors, and test data analysis identifies the SEU fault location. Two different ASIC designs realized in 180 nm CMOS technology are tested in this methodology and detection of SET prone cell is also illustrated.