VLSI Architecture for Implementing OTFS

Orthogonal Time Frequency Space (OTFS) modulation is proposed to support high-speed and reliable vehicular communication scenarios, which is a novel two-dimensional (2D) delay-Doppler domain modulation technique. Compared with traditional modulation schemes such as orthogonal frequency division multiplexing (OFDM), OTFS has displayed better performance in very high-mobility wireless channels. In this work, we have proposed the novel VLSI architecture for OTFS in the Additive White Gaussian Noise (AWGN) channel condition and shown the resource utilization report of our proposed architecture to implement on Field Programmable Gate Array (FPGA) board, along with the relationship between inputs and outputs of the OTFS signal in the delay-Doppler domain.