Performance evaluation of low power reconfigurable multiplier architectures using different adders for signal processing applications

The multimedia audio and video applications in battery operated portable hand-held devices need to perform numerous signal processing arithmetic operations which are highly multiplication intensive. The development of low power multiplier designs for signal processing applications will significantly contribute to the performance of portable mobile devices. This work provides emphasis on reconfigurability and approximation logic for increasing the power-saving and speed. A low power reconfigurable multi-precision approximate multiplier architecture is presented and its performance is compared against standard exact multiplier designs. Depending on the actual size of the input operands, the multiplier configures itself preventing un-necessary power loss. The impact of the wordlength and the adder used for adding partial products on the low power performance of the multiplier is studied by implementing variants of the proposed multiplier architecture. High boost filtering is performed on certain class of images and image quality is assessed. The approximate technique used does not deteriorate the image quality to notable extent.