71‐1: CMOS Backplane Technology and Its Challenge for µLEDoS AR/XR Display

This paper introduces the latest CMOS (Complementary Metal‐Oxide‐Silicon) backplane technology for µLEDoS AR/XR display engines. The backplane supports a display resolution of 1,280RGB x 720 and has been implemented on a 28nm Fully Depleted Silicon on Insular (FD‐SOI) CMOS process in order to meet the requirements such as performance, power, and pixel size. The area of a single pixel is 4.95µm x 4.95µm achieving higher than 5,000 PPI in RGB‐color mode. Each pixel contains 3 independent sub‐pixel drivers and one dependent driver assigned for a red LED. Each sub‐pixel driver includes a 10‐bit video SRAM memory, PWM (Pulse Width Modulation) control logic block, a constant current generator, and LED driver stage to drive red, green, or blue LEDs. The backplane also integrates necessary image processing functions such as De‐mura compensation, dead‐pixel compensation, and digital gamma generation. The top surface of the backplane wafer is also prepared for a wafer‐to‐wafer hybridization bonding between the CMOS wafer and an LED wafer.