Simulation of Silicon Field-Effect Conical GAA Nanotransistors with a Stacked SiO2/HfO2 Subgate Dielectric

The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO 2 /HfO 2 oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO 2 interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO 2 and HfO 2 layers.