MODELLING AND DESIGN OF SYMMETRICAL HALF-BRIDGE SUBMODULE MULTILEVEL CONVERTERS WITH SENSORLESS VOLTAGE BALANCE

Scalability and modularity are advantages of H-bridge-based multilevel converters, such as cascaded H-bridge converters. Nevertheless, they have higher conduction losses than their half-bridge-based counterparts due to the fact that each submodule requires two switches to conduct simultaneously in order to provide a current path. They also suffer from the complexity and costs associated with a high number of semiconductor switches, along with their drivers and peripheral circuits. This work presents revolutionary multilevel converters with symmetrical half-bridge submodules to minimize conduction losses and the number of active switch semiconductors. The symmetrical half-bridge submodule is simple, has fewer switches, and a bipolar voltage output. Additionally, using diodes and submodule parallelization, this study suggests a sensorless voltage balancing system that effectively eliminates capacitor voltage mismatch issues. This design can save dc capacitances by significantly reducing ripples in capacitor voltage, especially when multiple submodules are involved. Ultimately, the superiority of the suggested voltage balance scheme and multilayer converters is validated by modeling and experimental findings.