Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Adder is the critical component in any arithmetic application. Significant efforts have been made to improve their architecture. This paper introduces two novel symmetric designs for energy-efficient full adder (FA) employing Gate-Diffusion Input (GDI) logic. Our primary focus is achieving low-power operation with minimized area while ensuring full-voltage swing capability. The first design, referred to as AEG-FA, employs a novel strategy utilizing inverted and non-inverted Carry-inputs to produce complementary Carry-out and Sum outputs, thus achieving the desired performance characteristics. These techniques are then adapted in various combinations to construct adder architectures of higher bit widths, offering greater design flexibility across a spectrum of applications and reducing overall design complexity. In contrast, the second design, PEG-FA, follows a more conventional approach to minimize critical path delay and minimize switching activity within the GDI circuitry. This design prioritizes low-power consumption and high-speed operation while maintaining full voltage swing. Previous literature has noted challenges such as low-swing and high noise levels when operating adders at low supply voltages. Our proposed designs successfully address these issues, ensuring reliable operation even at lower voltages while maintaining signal integrity and driving capability. To assess the performance of the proposed FAs, we integrated them into an 8-bit ripple carry adder and optimized it for energy efficiency using 45 nm CMOS process technology. Comparative analysis with standard FA cells demonstrates improvements across all metrics. At the architecture level, the proposed adder provides power saving by 12.8%, 14.8%, and 11.4% than CMOS, hybrid, and other GDI logic, respectively, while exhibiting a 55% reduction in area.