Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication
Abstract In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardwar...
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| Veröffentlicht in: | International journal of electrical engineering & education 2024-04, Vol.61 (2), p.115-123 |
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| container_title | International journal of electrical engineering & education |
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| creator | Kareemullah, H Jose, Deepa Nirmal Kumar, P Radha, S |
| description | Abstract
In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardware complexity. The convergence strategy and steady state error performance are also increased without any additional hardware requirements. This is based on storing the past values of decision maker in a separate look up table and updating it time to time using parallel error multiplexer. Using this method, the results are very efficient by decreasing the power, area and logic utilization of the new architecture. If we include this concept as a hands-on experience, students can learn and also optimize the architecture easily. |
| doi_str_mv | 10.1177/0020720919833040 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_3055423861</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sage_id>10.1177_0020720919833040</sage_id><sourcerecordid>3055423861</sourcerecordid><originalsourceid>FETCH-LOGICAL-c177t-ae3170371728cf30f6df6d948076eb4efc6b4789e825f718fb2723f53fc061e03</originalsourceid><addsrcrecordid>eNp1UN1LwzAQD6LgnL77GPC5eknaJn0cc5vCwBd9Lml66TrWZiatY_-9LRUEQTg47vfF3RFyz-CRMSmfADhIDhnLlBAQwwWZcUggihOpLslspKORvyY3IexhnGM-I6dF6Y5d3VZU04M70Z325Ul7pB5LDHXVYkm1N7u6Q9P1Xh_oBFPrPMWyN7qrXTvA2H7V3rUNth0tzrQPY-bzehUVOgwZyYYa1zR9W0-OW3Jl9SHg3U-fk4_16n35Em3fNq_LxTYyw1FdpFEwCUIyyZWxAmxaDpXFCmSKRYzWpEUsVYaKJ1YyZQsuubCJsAZShiDm5GHKPXr32WPo8r3r_bBwyAUkScyFStmggkllvAvBo82Pvm60P-cM8vG9-d_3DpZosgRd4W_ov_pvbvJ6bg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>3055423861</pqid></control><display><type>article</type><title>Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication</title><source>SAGE Complete A-Z List</source><creator>Kareemullah, H ; Jose, Deepa ; Nirmal Kumar, P ; Radha, S</creator><creatorcontrib>Kareemullah, H ; Jose, Deepa ; Nirmal Kumar, P ; Radha, S</creatorcontrib><description>Abstract
In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardware complexity. The convergence strategy and steady state error performance are also increased without any additional hardware requirements. This is based on storing the past values of decision maker in a separate look up table and updating it time to time using parallel error multiplexer. Using this method, the results are very efficient by decreasing the power, area and logic utilization of the new architecture. If we include this concept as a hands-on experience, students can learn and also optimize the architecture easily.</description><identifier>ISSN: 0020-7209</identifier><identifier>EISSN: 2050-4578</identifier><identifier>DOI: 10.1177/0020720919833040</identifier><language>eng</language><publisher>London, England: SAGE Publications</publisher><subject>Complexity ; Hardware ; Lookup tables</subject><ispartof>International journal of electrical engineering & education, 2024-04, Vol.61 (2), p.115-123</ispartof><rights>The Author(s) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c177t-ae3170371728cf30f6df6d948076eb4efc6b4789e825f718fb2723f53fc061e03</cites><orcidid>0000-0002-6347-9384 ; 0000-0003-1564-7897</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://journals.sagepub.com/doi/pdf/10.1177/0020720919833040$$EPDF$$P50$$Gsage$$H</linktopdf><linktohtml>$$Uhttps://journals.sagepub.com/doi/10.1177/0020720919833040$$EHTML$$P50$$Gsage$$H</linktohtml><link.rule.ids>314,780,784,21810,27915,27916,43612,43613</link.rule.ids></links><search><creatorcontrib>Kareemullah, H</creatorcontrib><creatorcontrib>Jose, Deepa</creatorcontrib><creatorcontrib>Nirmal Kumar, P</creatorcontrib><creatorcontrib>Radha, S</creatorcontrib><title>Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication</title><title>International journal of electrical engineering & education</title><description>Abstract
In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardware complexity. The convergence strategy and steady state error performance are also increased without any additional hardware requirements. This is based on storing the past values of decision maker in a separate look up table and updating it time to time using parallel error multiplexer. Using this method, the results are very efficient by decreasing the power, area and logic utilization of the new architecture. If we include this concept as a hands-on experience, students can learn and also optimize the architecture easily.</description><subject>Complexity</subject><subject>Hardware</subject><subject>Lookup tables</subject><issn>0020-7209</issn><issn>2050-4578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNp1UN1LwzAQD6LgnL77GPC5eknaJn0cc5vCwBd9Lml66TrWZiatY_-9LRUEQTg47vfF3RFyz-CRMSmfADhIDhnLlBAQwwWZcUggihOpLslspKORvyY3IexhnGM-I6dF6Y5d3VZU04M70Z325Ul7pB5LDHXVYkm1N7u6Q9P1Xh_oBFPrPMWyN7qrXTvA2H7V3rUNth0tzrQPY-bzehUVOgwZyYYa1zR9W0-OW3Jl9SHg3U-fk4_16n35Em3fNq_LxTYyw1FdpFEwCUIyyZWxAmxaDpXFCmSKRYzWpEUsVYaKJ1YyZQsuubCJsAZShiDm5GHKPXr32WPo8r3r_bBwyAUkScyFStmggkllvAvBo82Pvm60P-cM8vG9-d_3DpZosgRd4W_ov_pvbvJ6bg</recordid><startdate>202404</startdate><enddate>202404</enddate><creator>Kareemullah, H</creator><creator>Jose, Deepa</creator><creator>Nirmal Kumar, P</creator><creator>Radha, S</creator><general>SAGE Publications</general><general>Sage Publications Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><scope>4T-</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-6347-9384</orcidid><orcidid>https://orcid.org/0000-0003-1564-7897</orcidid></search><sort><creationdate>202404</creationdate><title>Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication</title><author>Kareemullah, H ; Jose, Deepa ; Nirmal Kumar, P ; Radha, S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c177t-ae3170371728cf30f6df6d948076eb4efc6b4789e825f718fb2723f53fc061e03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Complexity</topic><topic>Hardware</topic><topic>Lookup tables</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kareemullah, H</creatorcontrib><creatorcontrib>Jose, Deepa</creatorcontrib><creatorcontrib>Nirmal Kumar, P</creatorcontrib><creatorcontrib>Radha, S</creatorcontrib><collection>CrossRef</collection><collection>Docstoc</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>International journal of electrical engineering & education</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kareemullah, H</au><au>Jose, Deepa</au><au>Nirmal Kumar, P</au><au>Radha, S</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication</atitle><jtitle>International journal of electrical engineering & education</jtitle><date>2024-04</date><risdate>2024</risdate><volume>61</volume><issue>2</issue><spage>115</spage><epage>123</epage><pages>115-123</pages><issn>0020-7209</issn><eissn>2050-4578</eissn><abstract>Abstract
In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardware complexity. The convergence strategy and steady state error performance are also increased without any additional hardware requirements. This is based on storing the past values of decision maker in a separate look up table and updating it time to time using parallel error multiplexer. Using this method, the results are very efficient by decreasing the power, area and logic utilization of the new architecture. If we include this concept as a hands-on experience, students can learn and also optimize the architecture easily.</abstract><cop>London, England</cop><pub>SAGE Publications</pub><doi>10.1177/0020720919833040</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0002-6347-9384</orcidid><orcidid>https://orcid.org/0000-0003-1564-7897</orcidid></addata></record> |
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| ispartof | International journal of electrical engineering & education, 2024-04, Vol.61 (2), p.115-123 |
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| language | eng |
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| subjects | Complexity Hardware Lookup tables |
| title | Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T04%3A07%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Adopting%20a%20low%20hardware%20redesigned%20architectural%20design%20for%20educational%20environment%20by%20using%20DFE-based%205G%20communication&rft.jtitle=International%20journal%20of%20electrical%20engineering%20&%20education&rft.au=Kareemullah,%20H&rft.date=2024-04&rft.volume=61&rft.issue=2&rft.spage=115&rft.epage=123&rft.pages=115-123&rft.issn=0020-7209&rft.eissn=2050-4578&rft_id=info:doi/10.1177/0020720919833040&rft_dat=%3Cproquest_cross%3E3055423861%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=3055423861&rft_id=info:pmid/&rft_sage_id=10.1177_0020720919833040&rfr_iscdi=true |